Activity 1.2.3 — Logic Levels & Digital Signals¶
Learning Objectives¶
By the end of this lesson, students will be able to:
- Define HIGH and LOW logic levels in terms of voltage ranges.
- Explain TTL voltage thresholds and noise margins.
- Describe pulse characteristics including rise time, fall time, and duty cycle.
- Understand why digital signals are resistant to noise.
Vocabulary¶
Vocabulary (click to expand)
| Term | Definition |
|---|---|
| Logic Level | The voltage range that represents a logical HIGH (1) or LOW (0). |
| HIGH (Logic 1) | The higher of two voltage levels used to represent a binary 1. |
| LOW (Logic 0) | The lower of two voltage levels used to represent a binary 0. |
| VOH | Minimum output voltage guaranteed to be recognized as HIGH by an input. |
| VOL | Maximum output voltage guaranteed to be recognized as LOW by an input. |
| VIH | Minimum input voltage guaranteed to be recognized as HIGH. |
| VIL | Maximum input voltage guaranteed to be recognized as LOW. |
| Noise Margin | The amount of additional noise a circuit can tolerate before switching states. |
| Rise Time (tr) | Time for a signal to transition from 10% to 90% of its final value. |
| Fall Time (tf) | Time for a signal to transition from 90% to 10% of its final value. |
| Duty Cycle | Percentage of time a signal is HIGH during one period. |
Part 1: Defining Logic Levels¶
What Are Logic Levels?¶
Logic levels are the specific voltage ranges that digital circuits use to represent binary values. Understanding these levels is essential because digital circuits must agree on what voltage means "on" (1) and what means "off" (0).
Standard Voltage Levels¶
| Logic State | Binary Value | Typical Voltage | Description |
|---|---|---|---|
| HIGH | 1 | +5V or +3.3V | Signal is present, circuit is active |
| LOW | 0 | 0V (ground) | No signal, circuit is inactive |
Why Not Just Any Voltage?¶
Digital circuits use specific voltage thresholds because:
- Consistency: All devices must agree on what constitutes HIGH and LOW
- Noise immunity: A margin between acceptable levels prevents false triggering
- Manufacturing tolerances: Real components have variations; thresholds account for this
Part 2: TTL Logic Levels¶
TTL (Transistor-Transistor Logic)¶
TTL is a type of digital circuit technology that was widely used historically. It defines specific voltage thresholds that are still used as standards today.
TTL Voltage Specifications¶
┌─────────────────────────────────────────────────────────────┐
│ TTL LOGIC LEVELS │
├─────────────────────────────────────────────────────────────┤
│ │
│ Supply Voltage (VCC) = 5V │
│ │ │
│5V │═══════════════════════════════════════════════════════│
│ │ VALID HIGH │
│ │ (2.4V - 5V) │
│ │ │
│2.4V├───────────────────────────────────────────────────────│ VOH (min output HIGH)
│ │ │
│ │ ┌───────────────────┐ │
│ │ │ UNDEFINED ZONE │ │
│2.0V├─────┤ (may be HIGH ├────────────────────────────│ VIH (min input HIGH)
│ │ │ or LOW) │ │
│ │ └───────────────────┘ │
│ │ │
│0.8V├───────────────────────────────────────────────────────│ VIL (max input LOW)
│ │ │
│ │ VALID LOW │
│ │ (0V - 0.4V) │
│ │ │
│0.4V├───────────────────────────────────────────────────────│ VOL (max output LOW)
│ │ │
│0V │═══════════════════════════════════════════════════════│
│ │ │
│GND └─────────────────────────────────────────────────────────│
│ │
└─────────────────────────────────────────────────────────────┘
Key TTL Specifications¶
| Parameter | Value | Meaning |
|---|---|---|
| VCC | 5V | Supply voltage |
| VOH | ≥ 2.4V (min) | Minimum output voltage for HIGH |
| VOL | ≤ 0.4V (max) | Maximum output voltage for LOW |
| VIH | ≥ 2.0V (min) | Minimum input voltage recognized as HIGH |
| VIL | ≤ 0.8V (max) | Maximum input voltage recognized as LOW |
Part 3: Noise Margin¶
What Is Noise Margin?¶
Noise margin is the maximum amount of noise (unwanted voltage interference) that can be added to a signal without causing an error. It is the "safety buffer" between what an output produces and what an input requires.
Calculating Noise Margin¶
Noise Margin HIGH (NMH):
Actually, the noise margin is calculated using the output levels the driver can guarantee:
NMH (how much noise can corrupt a HIGH before it's no longer reliable):
= VOH_min - VIH_min
= 2.4V - 2.0V
= 0.4V
NML (how much noise can corrupt a LOW before it's no longer reliable):
= VIL_max - VOL_max
= 0.8V - 0.4V
= 0.4V
Visualizing Noise Margin¶
┌─────────────────────────────────────┐
│ OUTPUT DRIVER │
│ │
Valid HIGH ──────┼──> 2.4V ──────────────────────────> │───> To Input
│ │
│ VOH output can range │
│ from 2.4V to 5.0V │
│ │
├─────────────────────────────────────┤
│ INPUT THRESHOLD ZONE │
│ (Undefined behavior!) │
│ │
├─────────────────────────────────────┤
│ │
│ VOL output can range │
Valid LOW ───────┼──> 0.4V ──────────────────────────> │───> To Input
│ from 0V to 0.4V │
│ │
└─────────────────────────────────────┘
Why Digital Is Noise-Resistant¶
Example showing noise resistance:
Without noise:
Input voltage: 4.8V → Clearly above 2.0V threshold → Reads as HIGH
With 1V of noise added:
Input voltage: 4.8V + 1.0V = 5.8V → Still above 2.0V threshold → Still reads as HIGH
The small voltage fluctuation does NOT change the logical value!
Key insight: Digital signals are noise-resistant because the thresholds create a "buffer zone." As long as the signal stays within the valid HIGH or valid LOW range, noise will not cause errors. This is one of the main advantages of digital over analog.
Part 4: Pulse Characteristics¶
Square Wave vs. Analog Wave¶
Digital signals are typically square waves with sharp transitions:
Digital Square Wave:
┌─────────┐ ┌─────────┐
│ │ │ │
HIGH ────┤ ├───────────────────┤ ├─────
│ │ │ │
└─────────┘ └─────────┘
────────── ──────────
rise fall rise fall
Analog Sine Wave:
~~~ ~~~
/ \ / \
/ \ / \
──────/ \────────────/ \────────────
Rise Time and Fall Time¶
Rise Time (tr): Time for the signal to go from 10% to 90% of its final value.
Fall Time (tf): Time for the signal to go from 90% to 10% of its final value.
100% ────────────────
90% ────────────────┐
│ <-- rise time (tr)
10% ────────────────┘
0% ─────────────────
│
└───> fall time (tf)
Good digital circuits have fast transitions (short rise/fall times).
Pulse Characteristics¶
A pulse is a single HIGH state followed by a LOW state (or vice versa).
Pulse Diagram:
Amplitude (A)
│
5V │┐ ┌─┐
││ Pulse width (PW) │ │
││ ──────────── │ │
0V ──┴┘ Period (T) │ ├────
←─────────────────→ │ │
│ │
└─┘
0 PW T
└───────────────────────────┘
Rising ┌────────────┐
edge │ │
│ │
└────────────┘
Falling edge
Key Parameters:
| Parameter | Symbol | Definition |
|---|---|---|
| Amplitude | A | Difference between HIGH and LOW voltage levels |
| Pulse Width | PW | Duration of the HIGH portion of the pulse |
| Period | T | Time for one complete cycle (HIGH + LOW) |
| Frequency | f | Number of cycles per second (f = 1/T) |
| Duty Cycle | D | Percentage of time the signal is HIGH (D = PW/T × 100%) |
Part 5: Calculating Period, Frequency, and Duty Cycle¶
Formulas¶
Period (T): T = 1/f (seconds)
Frequency (f): f = 1/T (Hertz, Hz)
Duty Cycle (D): D = (PW/T) × 100% (percentage)
Worked Example 1¶
A digital clock signal has a frequency of 1 kHz (1000 Hz). What is its period?
Worked Example 2¶
A square wave has a period of 20 ms. What is its frequency?
Worked Example 3¶
A signal has a period of 100 µs and a HIGH time of 30 µs. What is the duty cycle?
Duty Cycle Visual Comparison¶
50% Duty Cycle (square wave):
┌─────────┐ ┌─────────┐
│ │ │ │
─────┤ ├─────────┤ ├─────────
│ │ │ │
└─────────┘ └─────────┘
HIGH time = LOW time
25% Duty Cycle:
┌────┐ ┌────┐
│ │ │ │
─────┤ ├───────────────┤ ├─────────────
│ │ │ │
└────┘ └────┘
SHORT HIGH, LONG LOW
75% Duty Cycle:
┌───────────┐ ┌───────────┐
│ │ │ │
─────┤ ├─────────┤ ├─────────
│ │ │ │
└───────────┘ └───────────┘
LONG HIGH, SHORT LOW
Key insight: A 50% duty cycle means the signal is HIGH for exactly half the time—a true "square" wave. Many clock circuits use exactly 50% duty cycle, while other applications (like controlling motor speed) may use different duty cycles.
Summary¶
TTL Logic Level Quick Reference¶
| Parameter | Minimum | Maximum |
|---|---|---|
| Output HIGH (VOH) | 2.4V | 5.0V |
| Output LOW (VOL) | 0.0V | 0.4V |
| Input HIGH (VIH) | 2.0V | - |
| Input LOW (VIL) | 0.0V | 0.8V |
Noise Margin¶
- NMH (HIGH): VOH - VIH = 2.4V - 2.0V = 0.4V
- NML (LOW): VIL - VOL = 0.8V - 0.4V = 0.4V
Pulse Parameters¶
| Parameter | Formula | Units |
|---|---|---|
| Period (T) | 1/f | seconds |
| Frequency (f) | 1/T | Hertz (Hz) |
| Duty Cycle (D) | PW/T × 100% | percentage |
Key Reminders¶
- Logic levels define what voltage ranges mean HIGH (1) or LOW (0).
- TTL uses VCC = 5V with VIH = 2.0V and VIL = 0.8V.
- Noise margin is the safety buffer that prevents noise from corrupting signals.
- Digital signals are noise-resistant because they only distinguish between two states.
- Rise time and fall time measure how quickly a signal transitions.
- Duty cycle tells what percentage of time a signal is HIGH.
Practice Problem 1 — Noise Margin Calculation¶
For a circuit with VOH = 3.5V, VOL = 0.2V, VIH = 2.0V, and VIL = 0.8V, calculate the noise margins for HIGH and LOW.
Show Solution
Practice Problem 2 — Frequency and Duty Cycle¶
A clock signal has a frequency of 10 kHz and a duty cycle of 60%. Calculate: 1. Period of the clock 2. Duration of the HIGH time
Show Solution
Practice Problem 3 — Pulse Identification¶
A digital oscilloscope shows a signal that goes from 0V to 5V and back, staying at 5V for 25 ms during each 40 ms cycle. Identify: 1. Amplitude 2. Period 3. Frequency 4. Duty cycle
Show Solution
Part 1: Amplitude
Amplitude = HIGH voltage - LOW voltage
Amplitude = 5V - 0V = 5V
Part 2: Period
Period = 40 ms
Part 3: Frequency
f = 1/T
f = 1/0.040 s
f = 25 Hz
Part 4: Duty Cycle
D = (PW/T) × 100%
D = (25 ms / 40 ms) × 100%
D = 0.625 × 100%
D = 62.5%
Answers: Amplitude = 5V, Period = 40ms, Frequency = 25 Hz, Duty Cycle = 62.5%
Custom activity — adapted from PLTW Digital Electronics