Unit 2: Combinational Logic Design¶
This unit covers Boolean algebra, logic gates, Karnaugh maps, and combinational circuit design including encoders, decoders, and displays.
Lessons¶
| Code | Lesson | Topics |
|---|---|---|
| 2.1.0 | Intro to Logic & AOI Gates | AND, OR, INVERTER basics |
| 2.1.1 | Truth Tables | Truth tables, logic expressions |
| 2.1.2 | Circuit Analysis | Reading and analyzing AOI circuits |
| 2.1.3 | AOI Implementation | Building circuits from expressions |
| 2.1.4 | Boolean Algebra | Theorems, postulates, simplification |
| 2.1.5 | DeMorgan's Theorem | DeMorgan's, bubble pushing |
| 2.2.1 | Karnaugh Maps | K-maps, grouping, don't cares |
| 2.2.2 | Universal Gates | NAND/NOR as universal gates |
| 2.2.3 | AOI Conversion | Converting AOI to NAND/NOR |
| 2.2.4 | K-Map Grouping & POS | Product of Sums |
| 2.2.5 | Fireplace Control | Design challenge |
| 2.2.6 | Majority Vote | Design challenge |
| 2.3.1 | Hexadecimal & Octal | Number system conversions |
| 2.3.2 | Seven-Segment Display | BCD to 7-segment decoding |
| 2.3.3 | MUX & DEMUX | Multiplexers, demultiplexers |
| 2.3.4 | Two's Complement | Signed numbers, complement arithmetic |
| 2.3.5 | XOR/XNOR Gates | Exclusive OR/NOR gates |
| 2.3.6 | Binary Adders | Half adder, full adder, ripple carry |
| 2.4.1 | DOB 7-Segment | Design challenge project |