Activity 3.1.1 — D Flip-Flop¶
Learning Objectives¶
By the end of this lesson, students will be able to:
- Explain the difference between combinational and sequential logic circuits
- Describe the operation of an edge-triggered D flip-flop
- Interpret and create timing diagrams for D flip-flop operation
- Identify the inputs, outputs, and operation of the 74LS74 IC
Vocabulary¶
Vocabulary (click to expand)
| Term | Definition |
|---|---|
| Sequential Logic | Logic circuits where output depends on current inputs AND previous state (has memory) |
| Combinational Logic | Logic circuits where output depends only on current inputs (no memory) |
| Flip-Flop | A bistable circuit that stores one bit of data |
| Edge-Triggered | A flip-flop that changes state only on a clock transition (rising or falling edge) |
| Level-Triggered | A flip-flop that can change state while the clock is HIGH (or LOW) |
| Clock (CLK) | A periodic signal that synchronizes sequential circuits |
| Synchronous | Circuit changes occur in sync with the clock signal |
| Asynchronous | Circuit changes occur independent of the clock |
Part 1: Combinational vs Sequential Logic¶
Combinational Logic¶
In combinational logic circuits, the output depends only on the current inputs.
Examples: AND gate, OR gate, decoder, multiplexer
The output Y is determined purely by the present values of A and B.
Sequential Logic¶
In sequential logic circuits, the output depends on: 1. Current inputs 2. Previous state (history)
This "memory" capability makes sequential logic essential for computers, counters, and storage devices.
Examples: Flip-flops, counters, shift registers, memory
┌───────────────┐
Input ───┤ │
│ Sequential ├── Output
Clock ───┤ Circuit │
│ (has mem) │
└───────────────┘
Key insight: The key difference is that sequential circuits remember their previous state, while combinational circuits do not.
Part 2: The D Flip-Flop¶
The D (Data) flip-flop is the simplest type of edge-triggered flip-flop. It stores one bit of information.
Symbol and Pin Description¶
┌─────────────┐
D │ │
──────┤ D │
│ Flip-Flop ├── Q
CLK │ │ Q'
──────┤ │
PRE │ │
──────┤ │
CLR │ │
──────┴─────────────┘
Inputs¶
| Input | Name | Description |
|---|---|---|
| D | Data | The bit to be stored |
| CLK | Clock | Synchronizes state change |
| PRE | Preset | Asynchronous set (Q=1) |
| CLR | Clear | Asynchronous reset (Q=0) |
Outputs¶
| Output | Name | Description |
|---|---|---|
| Q | Output | The stored value |
| Q' | Complement | Inverse of Q |
Part 3: D Flip-Flop Operation¶
How It Works¶
On the rising edge (or falling edge, depending on design) of the clock pulse, the value at input D is transferred to output Q.
Simple rule: Q becomes whatever D is at the moment of the clock edge.
Truth Table¶
| D | CLK | Q (next state) | Operation |
|---|---|---|---|
| 0 | Rising Edge | 0 | Store 0 |
| 1 | Rising Edge | 1 | Store 1 |
| X | L/H Level | Q_no_change | No change |
| X | Falling Edge | Q_no_change | No change |
Key insight: The D flip-flop is "transparent" - it captures D and holds it until the next clock edge. Between clock edges, any changes to D are ignored.
Complete Truth Table (with PRE and CLR)¶
| PRE | CLR | D | CLK | Q | Operation |
|---|---|---|---|---|---|
| 0 | 1 | X | X | 1 | Preset (async set) |
| 1 | 0 | X | X | 0 | Clear (async reset) |
| 0 | 0 | X | X | X | Invalid (both active) |
| 1 | 1 | 0 | Rising Edge | 0 | Store 0 |
| 1 | 1 | 1 | Rising Edge | 1 | Store 1 |
| 1 | 1 | X | No Edge | Q | Hold current state |
Part 4: Timing Diagrams¶
A timing diagram shows how signals change over time.
Example Timing Diagram¶
D: ────┐ ┌───────┐ ┌───────┐ ┌────────
│ │ │ │ │ │
└───┘ └───────┘ └───────┘
CLK: ─────────┐ ┌────────────┐ ┌────────────┐ ┌──
│ │ │ │ │ │
└──┘ └──┘ └──┘
↑ ↑ ↑
rising edge rising edge rising edge
Q: ────┐ ┌───────┐ ┌────────
│ │ │ │ │
└─┘ └───────┘ └────────
(was 0) (becomes 1) (becomes 0)
Reading the Timing Diagram¶
- Before first clock edge: Q = 0 (initial state)
- At first rising edge: D = 1, so Q becomes 1
- Between edges: D changes but Q holds steady
- At second rising edge: D = 0, so Q becomes 0
Part 5: Edge-Triggered vs Level-Triggered¶
Level-Triggered (Latch)¶
A level-triggered D latch allows changes while CLK is HIGH:
D: ────┐ ┌─────────────┐
│ │ │
└───┘ └──────
CLK: ─────────────────────────────
┌────────────────────────┐
│ │
└────────────────────────┘
┌────────────────────────┐
Q: │ │
└────────────────────────
↑ changes with D ↑
(while CLK = HIGH)
Edge-Triggered (Flip-Flop)¶
An edge-triggered D flip-flop only changes on the clock transition:
D: ────┐ ┌─────────────┐
│ │ │
└───┘ └──────
CLK: ─────────────────────────────
┌────────────────────────┐
│ │
└────────────────────────┘
↑ ↑
rising edge rising edge
Q: ────┐ ┌───────┐
│ │ │ │
└─┘ └───────┘
↑ only changes at edges
Key insight: Edge-triggered flip-flops are preferred in most digital systems because they avoid "race conditions" where multiple signals try to change simultaneously.
Part 6: The 74LS74 Dual D Flip-Flop IC¶
The 74LS74 is a popular IC containing two independent D flip-flops.
Pinout Diagram¶
┌─────────────────────┐
1D ─┤ 1 14 ├─ VCC
1CLK─┤ 2 74LS74 13 ├─ 2CLR'
1PRE─┤ 3 12 ├─ 2PRE'
1Q ─┤ 4 11 ├─ 2CLK
1Q' ─┤ 5 10 ├─ 2D
GND ─┤ 6 9 ├─ 2Q
─┤ 7 8 ├─ 2Q'
└─────────────────────┘
Pin Description¶
| Pin | Function |
|---|---|
| 1D, 2D | Data inputs |
| 1CLK, 2CLK | Clock inputs (rising edge triggered) |
| 1PRE', 2PRE' | Asynchronous preset (active LOW) |
| 1CLR', 2CLR' | Asynchronous clear (active LOW) |
| 1Q, 2Q | Normal outputs |
| 1Q', 2Q' | Complementary outputs |
Part 7: Building a D Flip-Flop Circuit¶
Components¶
| Component | Quantity |
|---|---|
| Breadboard | 1 |
| 74LS74 IC | 1 |
| LED | 1 |
| 330 ohm resistor | 1 |
| Push button (SPST) | 1 |
| Jumper wires | As needed |
| +5V power supply | 1 |
Circuit Connections¶
- Power: Connect VCC (pin 14) to +5V, GND (pin 7) to GND
- Data input: Connect a switch or button to pin 2 (D input)
- Clock: Connect a push button to pin 3 (CLK)
- Outputs: Connect pin 5 (Q) to an LED with resistor to ground
Testing Procedure¶
- Apply power
- Set D input HIGH (1)
- Press and release the clock button
- Observe Q output - it should now be HIGH
- Set D input LOW (0)
- Press and release the clock button
- Observe Q output - it should now be LOW
Practice Problem — Predict the Output¶
Given the following D input and clock waveforms, draw the Q output waveform. Assume Q starts at 0.
D: ────┐ ┌───────┐ ┌────────────
│ │ │ │
└─────┘ └─────┘
CLK: ───────────┐ ┌──────────┐ ┌──────
│ │ │ │
└────┘ └────┘
↑ ↑ ↑
edge1 edge2 edge3
Q: ?
Show Solution
D: ────┐ ┌───────┐ ┌────────────
│ │ │ │
└─────┘ └─────┘
CLK: ───────────┐ ┌──────────┐ ┌──────
│ │ │ │
└────┘ └────┘
↑ ↑ ↑
edge1 edge2 edge3
Q: ─────────────────┐ ┌────────────
│ │
└─────┘
Explanation:
- Initial Q = 0
- At edge1: D = 1, so Q becomes 1
- Between edge1 and edge2: D changes but Q holds (no clock edge)
- At edge2: D = 0, so Q becomes 0
- After edge2: Q stays at 0
Practice Problem — Complete the Timing Diagram¶
Complete the Q output for this timing diagram:
D: ────┐ ┌───┐ ┌───────┐ ┌────
│ │ │ │ │ │
└───┘ │ └───────┘ └────
↑ │ ↑ ↑
change │ change change
CLK: ────────┐ ┌─────────┐ ┌──
│ │ │ │
└─────┘ └───────┘
↑ ↑ ↑
edge1 edge2 edge3
Q: ─────────────────────────────────────
(start at 0)
Show Solution
D: ────┐ ┌───┐ ┌───────┐ ┌────
│ │ │ │ │ │
└───┘ │ └───────┘ └────
↑ │ ↑ ↑
change │ change change
CLK: ────────┐ ┌─────────┐ ┌──
│ │ │ │
└─────┘ └───────┘
↑ ↑ ↑
edge1 edge2 edge3
Q: ────┐ ┌───────────────┐ ┌──
│ │ │ │
└───────────┘ └───┘
Step-by-step:
- Initial Q = 0
- edge1: D = 0 (sampled just before change) → Q = 0
- edge2: D = 1 → Q = 1
- edge3: D = 1 → Q = 1 (stays the same)
Summary¶
Key takeaways from this lesson:
- Sequential logic has memory (output depends on current inputs AND previous state)
- D flip-flops store one bit of data, capturing D at the clock edge
- Edge-triggered devices only change on clock transitions, not levels
- Timing diagrams show how signals change over time
- The 74LS74 is a common IC with two independent D flip-flops
Key Reminders¶
- D flip-flops capture the D input value at the moment of the clock edge
- Between clock edges, the output remains constant regardless of D changes
- PRE and CLR are asynchronous inputs (work without clock)
- Always connect unused inputs to a known state (HIGH or LOW)
- PRE' and CLR' are active LOW (they trigger when pulled LOW)
Custom activity — adapted from PLTW Digital Electronics