Activity 3.1.2 — JK Flip-Flop¶
Learning Objectives¶
By the end of this lesson, students will be able to:
- Describe the operation of a JK flip-flop and its four modes
- Interpret truth tables and timing diagrams for JK flip-flops
- Compare JK and D flip-flops in terms of capabilities
- Implement a JK flip-flop circuit and convert JK to D functionality
Vocabulary¶
Vocabulary (click to expand)
| Term | Definition |
|---|---|
| Toggle | When a flip-flop output switches between HIGH and LOW |
| Hold (No Change) | When a flip-flop maintains its current state |
| Set | When Q is forced to 1 (HIGH) |
| Reset | When Q is forced to 0 (LOW) |
| Complementary Outputs | Q and Q' are always opposite values |
Part 1: Introduction to the JK Flip-Flop¶
The JK flip-flop is more versatile than the D flip-flop. It has two control inputs (J and K) that allow four different operating modes.
Symbol and Pin Description¶
┌─────────────┐
J │ │
──────┤ │
K │ JK ├─ Q
──────┤ Flip-Flop │
CLK │ │ Q'
──────┤ │
PRE │ │
──────┤ │
CLR │ │
──────┴─────────────┘
Inputs and Outputs¶
| Input/Output | Description |
|---|---|
| J | Control input (set function) |
| K | Control input (reset function) |
| CLK | Clock input (edge-triggered) |
| PRE | Asynchronous preset (Q=1) |
| CLR | Asynchronous clear (Q=0) |
| Q | Normal output |
| Q' | Complementary output (always opposite of Q) |
Part 2: JK Flip-Flop Truth Table¶
The JK flip-flop has four operating modes based on J and K inputs:
| J | K | Q (next state) | Operation |
|---|---|---|---|
| 0 | 0 | Q | Hold (no change) |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Q' | Toggle |
Explanation of Each Mode¶
- Hold (J=0, K=0): Output stays the same - useful for pausing
- Reset (J=0, K=1): Output becomes 0 regardless of current state
- Set (J=1, K=0): Output becomes 1 regardless of current state
- Toggle (J=1, K=1): Output switches to opposite state - UNIQUE to JK!
Key insight: The toggle mode (J=K=1) is what makes JK flip-flops special. No other basic flip-flop can do this! This feature is essential for building counters.
Part 3: JK Flip-Flop vs D Flip-Flop¶
Comparison Table¶
| Feature | D Flip-Flop | JK Flip-Flop |
|---|---|---|
| Inputs | D, CLK | J, K, CLK |
| Hold mode | D = current Q | J=0, K=0 |
| Reset mode | D=0 | J=0, K=1 |
| Set mode | D=1 | J=1, K=0 |
| Toggle mode | NOT POSSIBLE | J=1, K=1 |
| Complexity | Simpler | More versatile |
Converting JK to D Flip-Flop¶
You can make a JK flip-flop behave like a D flip-flop by connecting J = K:
When J=K=0: Hold When J=K=1: Toggle (not useful for D)
To make JK work exactly like D: - Add external inverter: K = D', J = D
This creates: when D=1, J=1, K=0 (set); when D=0, J=0, K=1 (reset)
Part 4: Timing Diagrams¶
All Four Modes¶
J: ───────────────────────────────
K: ───────────────────────────────
CLK: ─────┐ ┌────┐ ┌────┐ ┌────
│ │ │ │ │ │
└──┘ └──┘ └──┘
↑ ↑ ↑ ↑
edge1 edge2 edge3 edge4
Q: ───┐ ┌──────────┐ ┌────
│ │ │ │
└───┘ └───┘
Hold Set Reset Toggle
Detailed Timing Analysis¶
Clock Edge 1 (J=0, K=0): Hold mode - Q maintains its previous state (whatever it was before)
Clock Edge 2 (J=1, K=0): Set mode - Q becomes 1
Clock Edge 3 (J=0, K=1): Reset mode - Q becomes 0
Clock Edge 4 (J=1, K=1): Toggle mode - Q switches to 1 (was 0)
Another Example¶
J: ────┐ ┌─────────────
│ │
└───────┘
↑ ↑ ↑
K: ────────────┐ ┌───────────
│ │
└─────┘
↑ ↑ ↑
CLK: ────────┐ ┌────────┐ ┌────
│ │ │ │
└────┘ └────┘
↑ ↑ ↑ ↑
edge1 edge2 edge3 edge4
Q: ──────────┐ ┌──────────┐ ┌──
│ │ │ │
└──────┘ └───┘
hold toggle hold toggle
Practice Problem¶
What is the state of Q at each edge?
| Clock Edge | J | K | Q (next) | Reason |
|---|---|---|---|---|
| 1 | 0 | 0 | ? | Hold |
| 2 | 1 | 1 | ? | Toggle |
| 3 | 0 | 0 | ? | Hold |
| 4 | 1 | 0 | ? | Set |
Show Solution
| Clock Edge | J | K | Q (next) | Reason |
|---|---|---|---|---|
| 1 | 0 | 0 | Q (prev) | Hold |
| 2 | 1 | 1 | Q' | Toggle (inverts) |
| 3 | 0 | 0 | Q (same) | Hold |
| 4 | 1 | 0 | 1 | Set |
Assume Q starts at 0: - Edge 1: Hold → Q=0 - Edge 2: Toggle → Q=1 - Edge 3: Hold → Q=1 - Edge 4: Set → Q=1 (already 1, stays 1)
Part 5: The 74LS76 Dual JK Flip-Flop IC¶
The 74LS76 contains two independent JK flip-flops with preset and clear inputs.
Pinout Diagram¶
┌─────────────────────┐
1J ─┤ 1 16 ├─ VCC
1CLK ─┤ 2 74LS76 15 ├─ 2CLK
1K ─┤ 3 14 ├─ 2K
1PRE─┤ 4 13 ├─ 2PRE
1CLR─┤ 5 12 ├─ 2CLR
1Q ─┤ 6 11 ├─ 2Q
1Q' ─┤ 7 10 ├─ 2Q'
GND ─┤ 8 9 ├─ 2J
└─────────────────────┘
Important Notes¶
- Clock is falling-edge triggered (different from 74LS74 which is rising-edge)
- PRE and CLR are active LOW (like 74LS74)
- J and K inputs must be stable before the clock edge
Part 6: Building JK Flip-Flop Circuits¶
Basic Test Circuit¶
Components: - 74LS76 JK flip-flop IC - Two push buttons for J and K inputs - One push button for clock - One LED for Q output - 330 ohm resistor - Jumper wires
Connections: 1. VCC to +5V, GND to ground 2. J input: push button to +5V (HIGH) or GND (LOW) 3. K input: push button to +5V or GND 4. CLK input: push button (make-or-break contact) 5. PRE' (pin 4) and CLR' (pin 5): connect to +5V (inactive) 6. Q output: LED through resistor to GND
Testing Each Mode¶
- Hold Test: Set J=0, K=0. Press clock. Q should not change.
- Set Test: Set J=1, K=0. Press clock. Q should become 1.
- Reset Test: Set J=0, K=1. Press clock. Q should become 0.
- Toggle Test: Set J=1, K=1. Press clock multiple times. Q should flip each time.
Practice Problem — Toggle Mode Application¶
Why is toggle mode important? Where is it used?
Show Solution
Toggle mode is ESSENTIAL for building:
1. BINARY COUNTERS
- Each JK flip-flop with J=K=1 toggles on every clock
- This divides the frequency by 2
- Cascading flip-flops creates a binary counter
2. FREQUENCY DIVIDERS
- One toggle flip-flop ÷2
- Two toggle flip-flops ÷4
- Three toggle flip-flops ÷8 (and so on)
3. DIVIDE-BY-N COUNTERS
- Using toggle with reset logic
- Can create any modulus counter
Without toggle, you cannot build efficient counters!
Practice Problem — Design Challenge¶
Design a circuit that makes the LED blink (toggle) once per second when given a 1 Hz clock input.
Requirements: - Use JK flip-flops - LED should change state every second - Clock input: 1 Hz square wave
Show Solution
Solution:
Connect a JK flip-flop with:
- J = 1 (HIGH)
- K = 1 (HIGH)
- Clock = 1 Hz input
With J=K=1, the flip-flop is in toggle mode.
On each clock rising edge (or falling edge for 74LS76),
the output Q will toggle.
If input clock is 1 Hz:
- Q toggles at 0.5 Hz (once every 2 seconds)
- That's too slow!
For 1 Hz toggle rate:
- Need frequency divider chain
Actually, if we want LED to blink ONCE per second:
- Input: 1 Hz
- Q toggles at 0.5 Hz (2 seconds per toggle)
- Not quite right...
Better approach: Use two flip-flops:
- FF1: J=K=1 (÷2) → 0.5 Hz output
- FF2: J=K=1 (÷2) → 0.25 Hz output
This gives 4 seconds per toggle - too slow.
The simplest solution:
- Use a single JK with toggle mode
- Input clock determines toggle rate
- For 1 Hz blink, input must be 2 Hz
OR: Use D flip-flop with inverted Q feedback:
- D = Q' (complement)
- This creates toggle behavior!
Part 7: JK with Preset and Clear¶
Understanding Asynchronous Inputs¶
PRE (Preset) and CLR (Clear) are asynchronous inputs that work independently of the clock.
Truth Table with PRE/CLR¶
| PRE' | CLR' | J | K | CLK | Q | Operation |
|---|---|---|---|---|---|---|
| 0 | 1 | X | X | X | 1 | Async Preset |
| 1 | 0 | X | X | X | 0 | Async Clear |
| 0 | 0 | X | X | X | X | Invalid! |
| 1 | 1 | 0 | 0 | Edge | Q | Hold |
| 1 | 1 | 0 | 1 | Edge | 0 | Reset |
| 1 | 1 | 1 | 0 | Edge | 1 | Set |
| 1 | 1 | 1 | 1 | Edge | Q' | Toggle |
Key insight: PRE' and CLR' are active LOW. Connect them to +5V when not in use. Never activate both at the same time!
Summary¶
Key takeaways from this lesson:
- JK flip-flop has four modes: hold, reset, set, and toggle
- Toggle mode (J=1, K=1) is unique to JK - D flip-flops cannot toggle
- JK can emulate D by connecting J = D and K = D'
- 74LS76 is a common dual JK flip-flop IC (falling-edge triggered)
- Toggle mode is essential for building counters and frequency dividers
Key Reminders¶
- J and K inputs must be stable before the clock edge
- PRE' and CLR' are active LOW (pull LOW to activate)
- Never activate PRE' and CLR' simultaneously
- 74LS76 is falling-edge triggered (some versions are rising-edge)
- Toggle mode (J=K=1) is key for counter design
Custom activity — adapted from PLTW Digital Electronics