Activity 3.2.1 — Asynchronous Counters¶
Learning Objectives¶
By the end of this lesson, students will be able to:
- Explain the operation of asynchronous (ripple) counters
- Design and analyze binary up and down counters
- Interpret timing diagrams for asynchronous counters
- Explain propagation delay and its effects on counter performance
- Design modulus (Mod-N) counters with reset logic
Vocabulary¶
Vocabulary (click to expand)
| Term | Definition |
|---|---|
| Counter | A sequential circuit that counts clock pulses |
| Asynchronous (Ripple) Counter | A counter where each flip-flop's output clocks the next flip-flop |
| Synchronous Counter | A counter where all flip-flops share a common clock |
| Binary Counter | A counter that counts in binary sequence (0000, 0001, 0010...) |
| Decade Counter | A counter that counts from 0 to 9 (10 states) |
| Modulus (Mod-N) | The number of states in a counter before it resets |
| Propagation Delay | The time delay between input change and output change in a gate/flip-flop |
Part 1: Introduction to Counters¶
A counter is a sequential logic circuit that counts the number of clock pulses. Counters are essential components in virtually every digital system:
- Digital clocks
- Timers
- Event counters
- Frequency dividers
- Address generators in memory systems
Types of Counters¶
| Type | Description |
|---|---|
| Asynchronous (Ripple) | Each flip-flop clocks the next one |
| Synchronous | All flip-flops share a common clock |
| Up Counter | Counts upward (0, 1, 2, 3...) |
| Down Counter | Counts downward (3, 2, 1, 0...) |
| Up/Down Counter | Can count in either direction |
Key insight: Counters are built using flip-flops in toggle mode (J=K=1). Each toggle divides the input frequency by 2.
Part 2: Binary Ripple Counter¶
A binary ripple counter is the simplest type of counter. Each flip-flop toggles when the previous flip-flop transitions from 1 to 0.
Circuit Diagram (4-bit Up Counter)¶
Clock ──▶ FF0 (LSB) ──▶ FF1 ──▶ FF2 ──▶ FF3 (MSB)
J=K=1 J=K=1 J=K=1 J=K=1
(toggle) (toggle) (toggle) (toggle)
Each flip-flop toggles on the negative (falling) edge of the previous flip-flop's Q output.
Complete Circuit with JK Flip-Flops¶
┌─────────────┐ ┌─────────────┐
Q0 ──┤ J Q ├────────┤ J Q ├─ Q1
│ FF0 │ │ FF1 │
J=K=1┤ K Q' │ Q0 ┤ K Q' │
└─────────────┘ └─────────────┘
CLK ▲ CLK ▲
│ │
│ Q0' │
└─────────────────────┘
┌─────────────┐ ┌─────────────┐
Q1 ──┤ J Q ├────────┤ J Q ├─ Q2
│ FF2 │ │ FF3 │
J=K=1┤ K Q' │ Q1 ┤ K Q' │
└─────────────┘ └─────────────┘
CLK ▲ CLK ▲
│ │
│ Q1' │
└─────────────────────┘
Part 3: Timing Diagram¶
4-Bit Binary Up Counter¶
Clock: ──┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
└───┘ └───┘ └───┘ └───┘ └───┘ └───┘ └───┘ └───┘ └───┘
↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Q0: ──┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌────
│ │ │ │ │ │ │ │ │ │ │ │
└───┘ └───┘ └───┘ └───┘ └───┘ └───┘ └───┘ └───┘
Q1: ──────────┐ ┌─────────┐ ┌──────────────
│ │ │ │
└─────────┘ └─────────┘
Q2: ────────────────────┐ ┌────────────────
│ │
└───────────────────┘
Q3: ────────────────────────────────────────┘
(ripple effect visible)
How It Works¶
| Clock | Q3 | Q2 | Q1 | Q0 | Decimal |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 1 |
| 2 | 0 | 0 | 1 | 0 | 2 |
| 3 | 0 | 0 | 1 | 1 | 3 |
| 4 | 0 | 1 | 0 | 0 | 4 |
| 5 | 0 | 1 | 0 | 1 | 5 |
| 6 | 0 | 1 | 1 | 0 | 6 |
| 7 | 0 | 1 | 1 | 1 | 7 |
| 8 | 1 | 0 | 0 | 0 | 8 |
| 9 | 1 | 0 | 0 | 1 | 9 |
| 10 | 1 | 0 | 1 | 0 | 10 |
| 11 | 1 | 0 | 1 | 1 | 11 |
| 12 | 1 | 1 | 0 | 0 | 12 |
| 13 | 1 | 1 | 0 | 1 | 13 |
| 14 | 1 | 1 | 1 | 0 | 14 |
| 15 | 1 | 1 | 1 | 1 | 15 |
| 16 | 0 | 0 | 0 | 0 | 0 (resets) |
Key insight: Q0 toggles on every clock (divide by 2). Q1 toggles when Q0 goes 1→0 (divide by 4). Q2 divides by 8, Q3 divides by 16. Each stage is half the frequency of the previous one.
Part 4: Down Counter¶
A down counter counts backward (15, 14, 13... 0). The key difference is using Q' (complement output) to clock the next flip-flop.
Down Counter Circuit¶
Clock ──▶ FF0 ──▶ Q0 ──▶ FF1 ──▶ Q1 ──▶ FF2 ──▶ Q2 ──▶ FF3 ──▶ Q3
J=K=1 J=K=1 J=K=1 J=K=1
Instead of using Q to clock the next stage, we use Q' (NOT Q)
Clock ──▶ FF0 ──▶ Q0' ──▶ FF1 ──▶ Q1' ──▶ FF2 ──▶ Q2' ──▶ FF3 ──▶ Q3
Timing Diagram (Down Counter)¶
Clock: ──┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
│ │ │ │ │ │ │ │ │ │ │ │ │ │
└───┘ └───┘ └───┘ └───┘ └───┘ └───┘ └───┘
↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
Q0: ──┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌────
│ │ │ │ │ │ │ │ │ │
└───┘ └───┘ └───┘ └───┘ └───┘ └───┘
Q1: ────────────┐ ┌─────────┐
│ │
└─────────┘
Q2: ────────────────────┐
│
└───────────
Q3: ────────────────────────────────────┘
Down Counter Truth Table¶
| Clock | Q3 | Q2 | Q1 | Q0 | Decimal |
|---|---|---|---|---|---|
| 0 | 1 | 1 | 1 | 1 | 15 |
| 1 | 1 | 1 | 1 | 0 | 14 |
| 2 | 1 | 1 | 0 | 1 | 13 |
| 3 | 1 | 1 | 0 | 0 | 12 |
| 4 | 1 | 0 | 1 | 1 | 11 |
| ... |
Part 5: Up/Down Counter¶
An up/down counter can count in either direction. It uses logic gates to select whether Q or Q' clocks the next stage.
Circuit Concept¶
When UP = 1: Use Q output to clock next stage (count up) When DOWN = 1: Use Q' output to clock next stage (count down)
Part 6: Propagation Delay Problem¶
The Ripple Effect¶
In asynchronous counters, each flip-flop is triggered by the previous flip-flop's output. This creates a "ripple" effect through the chain.
Clock: ──┐ ┌────────────────────────
│ │
└────┘
Q0: ──┐ ┌─┐ ┌──────────────
│ │ │
└────┘ │
│
(prop delay)│
│
Q1: ──────────┘ ┌────────────
│
└────────────
←─────── Ripple delay ────────
Problem¶
Each flip-flop has propagation delay (typically 10-50ns for TTL). In a 4-bit counter: - Total delay = 4 × propagation delay - If each flip-flop has 20ns delay, total = 80ns
Consequences¶
- Limited maximum clock frequency - The counter cannot count at arbitrarily high speeds
- Glitches - Short false pulses may appear in the output
- Synchronous counters solve this by using a common clock
Key insight: Asynchronous counters are simple but slow. Synchronous counters are faster but more complex. Choose based on your application requirements.
Part 7: Modulus (Mod-N) Counters¶
A modulus-N counter has N states before resetting. A binary counter is Mod-16 (counts 0-15).
Mod-10 (Decade) Counter¶
To make a Mod-10 counter (counts 0-9), we need to reset at count 10 (1010).
Reset Logic¶
Count 10 = Q3=1, Q2=0, Q1=1, Q0=0
We need a NAND gate that goes LOW when:
- Q3 = 1 AND Q1 = 1
NAND output ──▶ CLR (clear/reset)
Logic Gate Design¶
This NAND gate will reset the counter when it reaches 1010 (10).
Mod-6 Counter (Counts 0-5)¶
Practice Problem — Design a Mod-5 Counter¶
Design a modulus-5 counter (counts 0, 1, 2, 3, 4, then resets to 0).
- What binary value represents count 5?
- Which outputs will be HIGH at count 5?
- Draw the reset logic circuit.
Show Solution
1. Count 5 in binary = 0101 (Q2=1, Q1=0, Q0=1)
2. At count 5:
- Q2 = 1
- Q1 = 0
- Q0 = 1
3. Reset logic:
We need to detect when counter reaches 0101 (count 5)
Reset = Q2 AND NOT Q1 AND Q0
But this is more complex than needed.
Simpler approach: Use NAND to detect any combination
that only occurs at count 5.
Pattern at count 5: Q2=1, Q1=0, Q0=1
The simplest unique pattern that only appears at 5:
- Q2=1 AND Q0=1 (but Q1 must be 0 to avoid false trigger at other counts)
Better reset logic:
Q2 AND Q0' (this won't work - need unique pattern)
Let's check: Q2=1 appears at counts 4,5,6,7
Q0=1 appears at counts 1,3,5,7
Q2=1 AND Q0=1: counts 5 and 7 - NOT UNIQUE!
Solution: Use 3-input NAND or AND gate
Reset at count 5: Q2=1, Q1=0, Q0=1
Q2 ──┐
├─ AND ──▶ NAND ──▶ CLR'
Q1 ──┤ (invert Q1)
│
Q0 ──┘
Or simpler: Just detect Q2=1 and Q1=0:
When Q2 goes HIGH (at count 4), we wait to see if Q0 is also HIGH
At count 4: Q2=1, Q1=0, Q0=0 → NO reset
At count 5: Q2=1, Q1=0, Q0=1 → RESET!
Reset = Q2 AND NOT Q1 AND Q0
= Q2 • Q1' • Q0
Part 8: Common Counter ICs¶
74LS90 — Decade Counter (Mod-10)¶
The 74LS90 can count to 10 (0-9) and divide by 2, 5, or 10.
Features: - Counts 0-9 in BCD - Can be configured as divide-by-2 or divide-by-5
74LS93 — 4-Bit Binary Counter (Mod-16)¶
The 74LS93 is a 4-bit binary ripple counter.
Features: - Counts 0-15 (Mod-16) - Has separate flip-flops for modulo-2 and modulo-8 sections
Pinout Comparison¶
74LS90 74LS93
┌─────────────┐ ┌─────────────┐
A ─┤ 1 14├─ VCC B ─┤ 1 14├─ VCC
─┤ 2 7490 13├─ NC R0(1) ─┤ 2 7493 13├─ NC
─┤ 3 12├─ NC R0(2) ─┤ 3 12├─ NC
B ─┤ 4 11├─ Q3 A ─┤ 4 11├─ Q3
─┤ 5 10├─ Q2 B ─┤ 5 10├─ Q2
─┤ 6 9├─ Q1 C ─┤ 6 9├─ Q1
─┤ 7 8├─ Q0 A ─┤ 7 8├─ Q0
GND ─┴─────────────┘ GND ─┴─────────────┘
Summary¶
Key takeaways from this lesson:
- Counters use flip-flops in toggle mode (J=K=1) to divide frequency by 2
- Asynchronous counters cascade flip-flops with each output clocking the next
- Timing diagrams show the ripple effect through the counter stages
- Propagation delay limits maximum clock frequency in ripple counters
- Modulus counters use NAND gate reset logic to reset at specific counts
Key Reminders¶
- Each toggle flip-flop divides frequency by 2
- Use Q outputs for up counters, Q' outputs for down counters
- The ripple delay adds up: total delay = number of stages × propagation delay
- Mod-N counters use NAND gates to detect specific count values for reset
- Decades counters (Mod-10) are used in digital clocks
Custom activity — adapted from PLTW Digital Electronics