Activity 3.3.1 — Synchronous Counters¶
Learning Objectives¶
By the end of this lesson, students will be able to:
- Explain the difference between synchronous and asynchronous counters
- Design a synchronous counter using JK flip-flops
- Create excitation tables for flip-flops
- Analyze timing diagrams for synchronous counters
- Describe the advantages of synchronous counters over asynchronous counters
Vocabulary¶
Vocabulary (click to expand)
| Term | Definition |
|---|---|
| Synchronous Counter | A counter where all flip-flops share the same clock signal and change state simultaneously |
| Asynchronous Counter | A counter where each flip-flop is clocked by the output of the previous stage (ripple counter) |
| Excitation Table | A table that shows what input values are needed to produce a desired state transition |
| Propagation Delay | The time delay between an input change and the corresponding output change |
| Parallel Load | The ability to set all flip-flops to specific values simultaneously |
Part 1: Synchronous vs Asynchronous Counters¶
The Problem with Asynchronous Counters¶
In the previous lesson, you learned about asynchronous (ripple) counters. While these counters are simple to build, they have a significant problem: propagation delay accumulates through each flip-flop.
When you clock an 8-bit ripple counter: - First flip-flop changes immediately (0 ns delay) - Second flip-flop changes after first (10 ns delay) - Third flip-flop changes after second (20 ns delay) - And so on...
For an 8-bit counter, the last flip-flop might not change until 80 ns after the clock edge! This limits how fast the counter can operate.
Introducing Synchronous Counters¶
In a synchronous counter, ALL flip-flops receive the same clock signal at the same time. This means all outputs change simultaneously on every clock edge (or on specific clock edges, depending on the design).
Key differences:
| Feature | Asynchronous | Synchronous |
|---|---|---|
| Clock input | Only first flip-flop gets clock | All flip-flops share same clock |
| Output changes | Ripple through stages | All change simultaneously |
| Maximum speed | Limited by sum of all delays | Limited by single flip-flop delay |
| Design complexity | Simple | More complex |
Part 2: Designing Synchronous Counters with JK Flip-Flops¶
Step 1: Understanding JK Flip-Flop Behavior¶
JK flip-flops can be configured for different behaviors:
| J | K | Behavior |
|---|---|---|
| 0 | 0 | No change (hold) |
| 0 | 1 | Reset (Q = 0) |
| 1 | 0 | Set (Q = 1) |
| 1 | 1 | Toggle (Q = NOT Q) |
The key to synchronous counter design is: to make a flip-flop toggle on specific clock pulses, set J=K=1.
Step 2: The Excitation Table¶
An excitation table shows what J and K values are needed to produce each possible state transition:
| Current State (Q) | Next State (Q⁺) | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
Note: X means "don't care" - either 0 or 1 works.
Step 3: Designing a 4-Bit Synchronous Binary Up Counter¶
Let's design a counter that counts: 0000 → 0001 → 0010 → ... → 1111 → 0000
Step A: Determine when each flip-flop toggles
| Flip-Flop | Toggles When |
|---|---|
| Q0 (LSB) | Every clock pulse |
| Q1 | Q0 = 1 (before clock) |
| Q2 | Q0 = 1 AND Q1 = 1 |
| Q3 | Q0 = 1 AND Q1 = 1 AND Q2 = 1 |
Step B: Derive J and K inputs
| Flip-Flop | Condition for Toggle | J | K |
|---|---|---|---|
| Q0 | Always | 1 | 1 |
| Q1 | Q0 = 1 | Q0 | Q0 |
| Q2 | Q0·Q1 = 1 | Q0·Q1 | Q0·Q1 |
| Q3 | Q0·Q1·Q2 = 1 | Q0·Q1·Q2 | Q0·Q1·Q2 |
Step C: Circuit Implementation
Clock ──────┬─────┬─────┬─────┬─────
│ │ │ │
▼ │ │ │
┌─────┐ │ │ │
J0 ───┤ ├───┘ │ │
───┤ JK │ │ │
K0 ───┤ │ │ │
└─────┘ │ │
│ │ │
▼ ▼ │
┌─────┐ ┌─────┐ │
J1 ───┤ ├───┤ │ │
───┤ JK │ │ │ │
K1 ───┤ │ │ │ │
└─────┘ └─────┘ │
│ │
▼ ▼
┌─────┐ ┌─────┐
J2 ───┤ ├─────────┤ │
───┤ JK │ │ │
K2 ───┤ ├─────────┤ │
└─────┘ └─────┘
│ │
▼ ▼
┌─────┐ ┌─────┐
J3 ───┤ ├─────────┤ │
───┤ JK │ │ │
K3 ───┤ ├─────────┤ │
└─────┘ └─────┘
Part 3: Timing Diagram¶
Here's the timing diagram for a 4-bit synchronous counter:
Clock: ┌───┐ ┌───┐ ┌───┐ ┌───┐ ┌───┐ ┌───┐ ┌───┐ ┌───┐
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
└───┘ └───┘ └───┘ └───┘ └───┘ └───┘ └───┘ └───┘
↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
Q0: ┌───┐ ┌───┐ ┌───┐ ┌───┐
│ │ │ │ │ │ │ │
└───┘ └───┘ └───┘ └───┘
Q1: ┌───┐ ┌───┐ ┌───┐
│ │ │ │ │ │
└───┘ └───┘ └───┘
Q2: ┌───┐ ┌───┐
│ │ │ │
└───┘ └───┘
Q3: ┌───┐
│ │
└───┘
Key observation: All outputs change on the SAME clock edge - there is no ripple delay!
Key insight: In synchronous counters, the maximum clock frequency is limited only by the propagation delay of a single flip-flop, not the sum of all flip-flops. This makes synchronous counters much faster than asynchronous counters.
Part 4: The 74LS163 Integrated Circuit¶
Rather than building synchronous counters from scratch, engineers use integrated circuits like the 74LS163.
Features:¶
- 4-bit synchronous binary counter
- Built-in flip-flops and logic
- Parallel load capability
- Synchronous clear
- Cascadable (can chain together)
Pinout:¶
┌─────────────┐
CLR -│ |- VCC
CLK -│ 74LS163 |- QA
A -│ |- QB
B -│ |- QC
C -│ |- QD
D -│ |- RCO
LOAD -│ |- ENT
ENP -│ |- ENP
GND -│_____________│- ENT
Function Table:¶
| CLR | LOAD | ENT | ENP | Clock | Function |
|---|---|---|---|---|---|
| 0 | X | X | X | X | Clear (async) |
| 1 | 0 | X | X | ↑ | Parallel Load |
| 1 | 1 | 0 | X | X | Hold (disable count) |
| 1 | 1 | X | 0 | X | Hold (disable count) |
| 1 | 1 | 1 | 1 | ↑ | Count |
Part 5: Practice Problem — Design a 3-Bit Synchronous Up Counter¶
Problem Statement¶
Design a 3-bit synchronous binary up counter using JK flip-flops that counts: 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000
Steps to Solve¶
- Create a state transition table
| Current State | Next State |
|---|---|
| Q2 Q1 Q0 | Q2⁺ Q1⁺ Q0⁺ |
| 0 0 0 | 0 0 1 |
| 0 0 1 | 0 1 0 |
| 0 1 0 | 0 1 1 |
| 0 1 1 | 1 0 0 |
| 1 0 0 | 1 0 1 |
| 1 0 1 | 1 1 0 |
| 1 1 0 | 1 1 1 |
| 1 1 1 | 0 0 0 |
- Determine toggle conditions for each flip-flop:
- Q0 toggles on every clock: J0 = K0 = 1
- Q1 toggles when Q0 = 1: J1 = K1 = Q0
-
Q2 toggles when Q0 = 1 AND Q1 = 1: J2 = K2 = Q0·Q1
-
Draw the circuit diagram
Show Solution
Clock ──────┬─────┬─────┐
│ │ │
▼ │ │
┌─────┐ │ │
J0 ───┤ ├───┘ │
───┤ JK │ │
K0 ───┤ │ │
└─────┘ │
│ │
▼ ▼
┌─────┐ ┌─────┐
J1 ───┤ ├───┤ │
───┤ JK │ │ │
K1 ───┤ │ │ │
└─────┘ └─────┘
│ │
▼ ▼
┌─────┐ ┌─────┐
J2 ───┤ ├───┤ │
───┤ JK │ │ │
K2 ───┤ │ │ │
└─────┘ └─────┘
Toggle conditions: - Q0: Always toggles (J0 = 1, K0 = 1) - Q1: Toggles when Q0 = 1 (J1 = Q0, K1 = Q0) - Q2: Toggles when Q0 = 1 AND Q1 = 1 (J2 = Q0·Q1, K2 = Q0·Q1)
Summary¶
- Synchronous counters use a common clock for all flip-flops, eliminating propagation delay accumulation
- All outputs change simultaneously on the clock edge
- JK flip-flops with J=K=1 provide toggle mode
- Excitation tables determine what J/K values produce desired transitions
- The 74LS163 is a common 4-bit synchronous counter IC with parallel load
- Synchronous counters can operate at higher frequencies than asynchronous counters
Key Reminders¶
- In synchronous counters, all flip-flops share the SAME clock
- J=K=1 means "toggle on every clock edge"
- A flip-flop toggles when its J and K inputs are both HIGH
- Use AND gates to create conditional toggle logic
- Synchronous counters are faster but more complex than asynchronous counters
Custom activity — adapted from PLTW Digital Electronics