Activity 3.3.2 — 74LS193 Up/Down Synchronous Counter¶

Learning Objectives¶

By the end of this lesson, students will be able to:

Identify the pins and functions of the 74LS193 counter IC
Configure the 74LS193 for up counting, down counting, and parallel load
Cascade multiple 74LS193 counters to extend the count range
Design custom modulus counters using the 74LS193
Explain the difference between carry-out and borrow-out signals

Vocabulary¶

Vocabulary (click to expand)

Term	Definition
Parallel Load	Setting all flip-flops to specific values simultaneously using data inputs
Cascading	Connecting multiple counter ICs together to count to higher values
Carry-Out	A signal output that pulses HIGH when the counter reaches its maximum value
Borrow-Out	A signal output that pulses HIGH when the counter reaches its minimum value (down counting)
Modulus	The number of unique states in a counter (e.g., modulus-10 counts 0-9)
Decade Counter	A counter that counts from 0 to 9 (10 states)

Part 1: Introducing the 74LS193¶

The 74LS193 is a versatile 4-bit synchronous up/down counter. Unlike the 74LS163 (which only counts up), this IC can count in either direction and features parallel load capability.

Key Features:¶

4-bit binary counter (0-15)
Up counting with separate clock input
Down counting with separate clock input
Parallel load (preset to any value)
Asynchronous clear (master reset)
Cascadable with carry-out and borrow-out outputs

Pinout Diagram:¶

        ┌─────────────┐
   CPU -│             |- VCC (5V)
   CPD -│             |- Q0 (QA)
   D0  -│             |- Q1 (QB)
   D1  -│   74LS193   |- Q2 (QC)
   D2  -│             |- Q3 (QD)
   D3  -│             |- TCU (Carry Out)
  MR   -│             |- TCB (Borrow Out)
  PL  -│_____________|- GND

Pin Definitions:¶

Pin	Name	Function
CPU	Clock Up	Clock input for counting UP (rising edge)
CPD	Clock Down	Clock input for counting DOWN (rising edge)
D0-D3	Data Inputs	Input pins for parallel load
Q0-Q3	Outputs	Counter output bits
MR	Master Reset	Asynchronous clear (active HIGH)
PL	Parallel Load	Load data inputs when pulsed LOW
TCU	Terminal Count Up	Carry-out, goes HIGH when counting to 15
TCB	Terminal Count Down	Borrow-out, goes HIGH when counting to 0

Part 2: Function Table¶

The 74LS193 has several operating modes controlled by MR, PL, and the clock inputs:

MR	PL	CPU	CPD	Function
1	X	X	X	Clear (all outputs = 0000)
0	0	X	X	Parallel Load (D3-D0 → Q3-Q0)
0	1	↑	1	Count UP (0000 → 1111 → 0000)
0	1	1	↑	Count DOWN (1111 → 0000 → 1111)
0	1	1	1	Hold (no change)

Important Notes: - MR (Master Reset) is active HIGH - set to 0 for normal operation - PL (Parallel Load) is active LOW - set to 1 for counting, pulse LOW to load - Both clock inputs should be held HIGH when not in use

Part 3: Basic Operations¶

Operation 1: Up Counting¶

To count UP from 0 to 15:

Set MR = 0 (disable clear)
Set PL = 1 (enable counting)
Hold CPD = 1 (disable down clock)
Apply clock pulses to CPU

MR ────[0V]
PL ────[5V]
CPD ───[5V]
CPU ───[Clock pulses]

Output sequence: 0000 → 0001 → 0010 → ... → 1111 → 0000

Operation 2: Down Counting¶

To count DOWN from 15 to 0:

Set MR = 0
Set PL = 1
Hold CPU = 1 (disable up clock)
Apply clock pulses to CPD

MR ────[0V]
PL ────[5V]
CPU ───[5V]
CPD ───[Clock pulses]

Output sequence: 1111 → 1110 → 1101 → ... → 0000 → 1111

Operation 3: Parallel Load¶

To preset the counter to a specific value:

Set MR = 0
Apply desired values to D0-D3
Pulse PL LOW, then HIGH

D3 D2 D1 D0 = [Desired value]
PL ────[LOW]───[HIGH]

Output changes to match data inputs

Operation 4: Asynchronous Clear¶

To reset all outputs to 0000:

MR ────[HIGH]

All outputs immediately become 0000

Part 4: Cascading Counters¶

To count beyond 15, cascade multiple 74LS193 ICs together.

Connecting Two 74LS193 Chips:¶

                    ┌──────────────┐
     CPU ──────────▶│              │
     (clock)       │  74LS193 #1  ├─── Q0 ──▶
                    │   (ones)    ├─── Q1 ──▶
                    │              ├─── Q2 ──▶
                    │              ├─── Q3 ──▶
                    │              │
     TCU ───────────┤              ├───▶ to CPD #2
                    └──────────────┘

                    ┌──────────────┐
    (from TCU #1) ─▶│              │
                    │  74LS193 #2  ├─── Q0 ──▶
                    │   (tens)    ├─── Q1 ──▶
                    │              ├─── Q2 ──▶
                    │              ├─── Q3 ──▶
                    └──────────────┘

Cascading Rules:¶

Up counting: Connect TCU (carry-out) of lower chip to CPD (down clock) of upper chip
Down counting: Connect TCB (borrow-out) of lower chip to CPU (up clock) of upper chip
All chips share the same CPU or CPD clock signal
Set PL and MR pins identically for all chips

Part 5: Designing Custom Modulus Counters¶

Example 1: Decade Counter (Counts 0-9)¶

A decade counter counts from 0 to 9, then resets to 0.

Design Approach:

Count from 0 to 9 (binary: 0000 to 1001)
When output = 1010 (10), reset to 0000

Implementation:

Use the parallel load function
Detect when count reaches 10 (Q3=1, Q2=0, Q1=1, Q0=0)
Use a NAND gate to detect 1010 and trigger PL

Detection logic:
Q3·Q2·Q1·Q0 = 1·0·1·0 = 0 (use NOR or detect NOT 1010)

Better approach: Detect count = 10 using:
Q3 = 1, Q2 = 0, Q1 = 1, Q0 = 0

Use: PL = NOT(Q3 AND NOT Q2 AND Q1 AND NOT Q0)
    PL = Q3' + Q2 + Q1' + Q0 (De Morgan)

Example 2: Count to 60, Then Reset¶

To create a counter that counts 0-59 (like seconds or minutes):

Use two 74LS193 chips
Ones counter: counts 0-9, then carries to tens
Tens counter: counts 0-5, then resets

Connection:

Ones counter: Normal up counting, reloads to 0 on carry
Tens counter: Increments when ones counter carries, resets at 6

Ones counter resets at 10 (1010)
Tens counter increments when ones = 9 and clock pulses

Combined: 00 → 01 → ... → 59 → 00

Part 6: Practice Problem — Design and Test¶

Problem Statement¶

Design a modulus-12 counter using the 74LS193 that counts from 0 to 11, then resets to 0.

Required Steps:¶

Determine what binary value triggers the reset
Design the detection logic
Explain how to wire the circuit
Determine the clock frequency if you want 1 Hz output rate

Show Solution

Step 1: Binary value for 12

12 in binary = 1100 (Q3=1, Q2=1, Q1=0, Q0=0)

Step 2: Detection logic

When Q3=1, Q2=1, Q1=0, Q0=0, we want to reset to 0000.

Using parallel load (PL is active LOW): - When count = 12, pulse PL LOW to load 0000

Detection: Q3 AND Q2 AND NOT Q1 AND NOT Q0

Step 3: Circuit wiring

Data inputs D0-D3 = 0000 (load zero)
Detection circuit output → PL pin
When count reaches 12, PL goes LOW, loads 0000

Step 4: Clock frequency

If 1 Hz output rate desired: - Counter goes 0→1→2→...→11→0 = 12 states per cycle - Clock frequency = 12 Hz for 1 Hz output rate

Summary¶

The 74LS193 is a versatile 4-bit up/down synchronous counter
Separate clock inputs for up (CPU) and down (CPD) counting
Parallel load allows preset to any value
Cascading extends count range by connecting carry/borrow outputs
Custom modulus counters use parallel load to reset at specific values
Carry-out (TCU) pulses HIGH when counting to max (15)
Borrow-out (TCB) pulses HIGH when counting to min (0)

Key Reminders¶

PL (Parallel Load) is active LOW
MR (Master Reset) is active HIGH
Always hold unused clock input HIGH
Connect TCU to CPD for cascading up counters
Use parallel load to create custom reset points

Custom activity — adapted from PLTW Digital Electronics